1. Field of the Invention
This invention relates to microprocessors. In particular, the invention relates to virtual memory.
2. Description of Related Art
Memory management subsystem is one of the most important parts of the operating system (OS). Virtual memory is a technique within the memory management subsystem to allow the processor to access a larger memory space than the physical memory that actually exists in the processor system. To accomplish this, the memory management subsystem has to provide a translation or address mapping mechanism to map the virtual address space into the physical address space.
A typical OS manages and controls a number of processes concurrently. Each process has its own virtual address space. These virtual address spaces are usually separate from each other to prevent overlapping program or data. The OS has to maintain a page table to store the mapping information for each process. When the number of processes in the system becomes large, or the number of address mappings is high, the overhead of managing virtual address mappings can become a significant performance limiter in large computer systems, especially when managing sparse 64-bit or larger address spaces.
A number of prior art techniques exist for virtual mapping. One technique uses a linear or hashed page table which is laid out in the memory contiguously. This technique requires a large physical memory space. Another technique provides global sharing of page tables for a set of translations (global bit). While this technique allows the OS to map globally shared objects efficiently, it does not provide mechanisms for mapping sparse large 64-bit or larger user address spaces efficiently.
Therefore there is a need in the technology to provide a simple and efficient method to perform virtual memory mapping.
The present invention relates to a method and apparatus to map virtual memory space. In brief, one embodiment of the apparatus comprises a region register file and a virtual page table look-up circuit. The region register file provides a region identifier for a virtual address in the virtual memory space. The virtual address includes a virtual region number and a virtual page number. The virtual page table look-up circuit is coupled to the region register file to generate a page table entry (PTE) virtual address from virtual address parameters. The virtual address parameters include the the virtual address.